Streamlining Testbench Development with QVIP

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May 30, 2023, 12:00 PM - 1:00 PM
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Faïçal Chtourou, Siemens EDA

Faïçal Chtourou is an European application engineer at Siemens EDA, specialized in Digital functional verification tools and methodology.

His background includes 10+ years of experience verifying complex SOC in various markets (HPC, Automotive, Flash memory); he has a strong interest in flow automation and RTL quality improvement. Faïçal holds an MS degree in Microelectronics and Telecommunication from Polytech Marseille, France.


  • May 30, 2023, 12:00 PM - 1:00 PM


The Wilson Research Group study of 2022 has revealed that verification activity takes up a significant proportion of the effort required for FPGA/ASIC projects, ranging from 40 to 60 percent. The study has also identified that more than 30 percent of verification engineers face challenges creating enough tests to verify the design adequately.

In this upcoming webinar, Faïçal Chtourou will demonstrate how Siemens EDAs Questa VIP solution can help reduce this burden by accelerating your project, enhancing the design quality, and mitigating the risk.

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